System-On-Chip (SoC) and integrated circuit (IC) designs are increasingly complex, and more and more processors are integrated into SoCs/ICs to perform increasingly varying and complex functionalities. Also, multiple SoCs/ICs are commonly linked together for advanced applications. Multiple processors/SoCs/ICs can be involved in performing certain tasks, and each processor/SoC/IC can be dependent on one or more others to complete the tasks.
To ensure continuous and smooth performance of the processors/SoCs/ICs by avoiding lockups and crashes, these components are thoroughly debugged before they are made available for use and sale. Debugging logic is traditionally designed to facilitate single or multiprocessor debug functions on a single SoC. Functions such as halting and resuming of execution of a single processor core, synchronized halting and resuming of multiple processor cores, processor trace enablement and disablement, trace capture enablement are all examples of intra-SoC debug functions. It should be noted that on current complex SoCs that debug functions extend far beyond processor debugging. Other functions such as distributed performance monitoring, hardware (non-processor) trace functions, driver level trace units such as ARM's system trace macrocell, deterministic traffic injection (busses, state machines, peripheral interfaces) are other (non-processor) examples of intra-SoC debug functions.
Currently cross triggering hardware is used to provide low latency signaling from one SoC debug function to another SOC debug function. Cross trigger blocks such as ARM's cross trigger interface (CTI) are preconfigured by a debug agent (software agent or external debugger) to route a given set of trigger sources to a given set of trigger destinations. Functions such as stopping trace collection in a circular buffer upon detection of fatal system event (e.g. watchdog expiry), enabling of distributed performance monitors, synchronized halting of multiple processors may all be facilitated via preconfiguration of one or more SoC cross trigger blocks (e.g. ARM CTI). To facilitate cross trigger amongst two or more SoCs (e.g. synchronized processor resume of two processors residing on different SoCs), the current technique is to route a discrete number of cross trigger wires via shared or dedicated pins on each SoC. When multiple cross trigger use cases are required to run concurrently, the number of pins between SOCs becomes prohibitively expensive so another technique is needed.